(1) Field of the Invention
The present invention relates to a solid state image sensing apparatus with a Charge Coupled Device (CCD) that has an overflow drain (OFD) structure and its driving method.
(2) Description of the Related Art
Recently, electric devices for recording images such as digital cameras, digital video cameras and cellular phones with a camera have become popular, and image sensors such as CCD image sensors have been refined as resolution becomes higher.
FIG. 1 is a block diagram showing the structure of a conventional CCD solid state image sensing apparatus that is disclosed in patent literature and the like. In the figure, the solid state image sensor 10 comprises a plurality of photodiodes 11 that are aligned two-dimensionally, a plurality of readout gate units 12, a plurality of vertical CCDs 13, a horizontal CCD 15, an output amplifier 16, a substrate bias generating circuit 20 and a transistor Q1. The figure also shows a transistor Q2 and resistance R1 to R3 as a circuit for modulating the bias voltage Vsub of the semiconductor substrate (called a substrate bias from here) of the solid state image sensor.
The patent literature discloses a technique where the decrease in the amount of saturation signal charge at the time of reading out a frame is estimated and the expected decrement is previously increased. Reading out frames here means reading out fields field by field. In other words, signal charge in each odd line and signal charge in each even line separately with the mechanical shutter (that is not shown in the figure) closed after exposure time elapses, and the method is often used in the case of obtaining a single still picture.
A plurality of photodiodes 11 are aligned two-dimensionally so as to form an imaging area 14 in FIG. 1. Each photodiode 11 transforms the incoming light into signal charge according to the amount of light and stores the signal charge. Each photodiode 11 comprises photodiodes, for example, pn-junction photodiodes. When readout pulse XSG is applied to the readout gate unit 12, the signal charge stored in the photodiodes 11 that forms vertical lines are read out to the vertical CCDs 13.
Each vertical CCD 13 is set for each vertical line of the photodiodes 11 and vertically transfers the read out signal charge from each photodiode 11 to a horizontal CCD 15 via a read out gate unit 12. In the case of a solid state image sensor of an interline transfer (IT), vertical transmission gate electrodes, which are for performing a transmission driving by four-phase vertical transmission clock φV1 to φV4 or the like, that are repeatedly aligned in each vertical CCD 13, and signal charge that is read out from the photodiodes 11 are transferred in the vertical direction in sequence. In this way, a plurality of vertical resistors 13 outputs signal charge of a single scanning line to the horizontal resistor 15 in a horizontal blanking period. In the four-phase vertical transmission clock φV1 to φV4, φV2 in the second phase and φV4 in the fourth phase may take two values, one of which is a low level value for vertical transmission and the other one of which is a middle level value. In contrast, as vertical transmission gate electrodes corresponding to the first phase and the third phase also serve as the readout gate electrode of the readout gate unit 12, the vertical transmission clock φV1 and φV3 may take three values; they are a low level value, a middle level value and a high level value respectively. The third one, that is, the high level pulse becomes the reading out pulse XSG which is given to the readout gate unit 12.
The horizontal CCD 15 horizontally transfers charges of a single line that are transferred from a plurality of vertical CCDs 13 in the horizontal blanking period in sequence within a single horizontal scanning period and outputs them via the output amplifier 16. For example, this horizontal CCD 15 driven by the two phase horizontal transmission clock φH1 and φH2 transfers signal charge for a single line that are transferred from several vertical CCDs 13 in the horizontal direction in sequence in the horizontal scanning period after the horizontal blanking period.
The output amplifier 16 transforms the signal charge that is horizontally transferred by the horizontal CCD 15 into voltage signals in sequence and outputs them.
The substrate bias voltage generating circuit 20 generates the substrate bias voltage Vsub and applies it to the substrate 17 via the transistor Q1. This substrate bias Vsub is set as the first bias voltage when the transistor Q2 is OFF or is set as the second bias voltage with a lower voltage when the transistor Q2 is ON under the control of the VsubCont signal.
The above-mentioned solid state image sensor 10 is formed on the semiconductor substrate 17 (called substrate from here). Various kinds of timing signals such as substrate shutter pulse φ SUB for sweeping the signal charge that is stored in the photodiodes 11 to the substrate 17 are applied to the substrate 17. Note that the function of the substrate shutter function by the substrate shutter pulse φ SUB is called an electronic shutter.
FIG. 2 is a diagram showing the distribution of potential in the substrate depth direction of the photodiodes 11. The amount of charge of the signal charge “e” that is stored in the photodiodes 11 is determined based on the height of the potential barrier of the overflow barrier (OFB). In other words, the overflow barrier (OFB) is the key for determining the amount of the saturation signal charge Qs that are stored in the photodiodes 11. In the case where the amount of stored charge exceeds this amount of saturation signal charge Qs, the excessive amount of charge overflow to the substrate 17 side over the potential barrier. The potential of the overflow barrier OFB in this vertical overflow drain structure can be controlled by the overflow drain bias, that is, the substrate bias Vsub. In other words, the height of the barrier can be controlled by the substrate bias Vsub.
FIG. 3 is a time chart showing the operational timing of the solid state image sensor in reading out frames as well as controlling the substrate bias Vsub. The figure shows open/close state of the mechanical shutter, the substrate bias Vsub (substrate voltage in the figure) and vertical transmission clock φV1 and φV3 that are applied to the reading out gate electrodes between the photodiodes 11 and the vertical CCDs 13. High-level pulses respective for the vertical transmission clock φV1 and φV3 is a readout pulse XSG that is given to the readout gate electrodes.
In the monitor period, an image is read out from the solid state image sensor so as to display it on a view finder or a liquid monitor with the mechanical shutter opened and it is displayed as a moving picture (the mode is called high-speed moving picture imaging mode).
Also, in response that a user operates the shutter, imaging a still picture by reading out a frame starts (the mode for displaying is called still picture imaging mode) with a help of the mechanical shutter. First, a plurality of substrate shutter pulses φ SUB (substrate shutter voltage pulses in the figure) are applied to the substrate bias Vsub. The substrate shutter is for sweeping all the signal charge of the photodiodes 11 out to the substrate 17 by eliminating the effect of the overflow barrier (refer to FIG. 2) in response that the φ SUB makes the substrate bias Vsub higher. The completion of applying substrate pulses makes the storage amount of signal charge of photodiodes 11 “0”. The period starting from the time of the completion of applying these substrate shutter pulses to the time of the closure of the mechanical shutter is the exposure period. Subsequently, the following periods are set in sequence: a high-speed sweeping period for previously sweeping out signal charge in the vertical CCDs 13, the first field output period, a high-speed sweeping period, the second field output period and an invalid data output period. In the respective heads of the readout periods of the first field and the second field, the readout pulse XSG that is superimposed on φV1 and φV3 reads out signal charge in the first field and the second field from the photodiodes 11 and applies them to the vertical CCDs. Through the invalid data output period that succeeds the second field output period, the second cycle starts from the monitor output period.
The first bias voltage is applied to the substrate bias Vsub in the high-speed moving picture mode (that is, during the monitoring period). As shown in FIG. 3, the first bias voltage is switched to the second bias voltage in the still picture mode (that is called a substrate bias modulation). The second bias voltage is lower than the first bias voltage, which makes the height of the overflow barrier (OFB) taller in the case of using the second bias voltage and brings the increase in saturation signal charge Qs. The second bias voltage is used in the period starting from the exposure period to the invalid data output period in the figure, at least the second field output period should be included.
The patent literature 1 discloses the modulation of the substrate bias and its timing more specifically.
[Patent literature 1] Japanese Laid-Open Patent application No. 1998-150183.
[Non-patent literature 1] Specification No. ICX232BQ “Diagonal 5 mm (Type 1/3.6) Frame Readout CCD Image Sensor with Square Pixel for Color Cameras” published by SONY Co.,
[online] Internet <URL: http://www.sony.co.jp/{tilde over ( )}semicon/Japanese/img/sonyj01/e6801383.pdf> (search result as of Apr. 23, 2003)
However, in the case where the substrate bias is modulated before the exposure finishes, while the conventional technique makes it possible to estimate the decrement of saturation signal charge Qs that occurred at the time period when light is cut off by the mechanical shutter and compensate the decrement, there is a need to make the height of the overflow barrier (OFB) by the second bias voltage lower than that of the readout gate barrier in order to avoid blooming during all the periods. Thus, the amount of the bias modulation is limited. Therefore, there is no possibility that the amount of saturation signal charge Qs increases a lot.
Also, modulating the substrate bias after exposure makes the overflow barrier (OFG) at readout time higher than the one at charge storage time, which makes it possible to narrow the difference between the amount of saturation charge Qs in the first field and the one in the second field. However, no increase in the amount of saturation signal charge Qs is observed because the overflow barrier (OFG) at charge storage time is not made higher.
The conventional technique only avoids the deterioration in properties that is caused by the decrease in the amount of saturation signal charge in proportion to the elapsed time. As the recent refinement of the solid state image sensing apparatus resulted in the refinement of the surface of a photodiode, the surface of a gate electrode and the like, there emerges a need to improve the conversion quantum efficiency of a photocathode and to enhance the sensitivity as well as enlarge the capacity of the amount of saturation signal charge.